Electrics-cooling has an interesting research paper from a couple years back that I thought timely to bring up for discussion again. With larger CPU heat spreaders on the horizon, decreasing the forces needed to mount a heatsink and reducing the thermal compound gap size are very relevant points to consider. The paper is titled; "Mini- and Microchannels in Thermal Interfaces: Spatial, Temporal, Material, and Practical Significance" by Dr.Brian Smith, Ph.D. It's an interesting read, here's a short excerpt.
"We have shown that paste interfaces can be formed with lower pressure and thinner bondlines by hierarchically nested channel (HNC) structures [5-7]. The reduction in thermal resistance and assembly loads is attractive for automotive, power electronics, optical, RF, and microprocessor packaging; enabling higher-power operation at lower junction temperature.
The channels relieve pressure during the assembly squeeze, offsetting the effective non-Newtonian viscosity increase due to particle loading. The assembly dynamics are described by Stefan (squeeze) flow with a crucial modification: The square interface in electronics packages causes the fluid flow to bifurcate along the diagonal because the flow path to the edge of the interface is shorter (Figure 1). The bifurcation also causes local variation in particle fill factor that leads to spatial keff,TIM variations or electrical resistivity variations for electrically-conductive formulations as the particles may be suspended at the bifurcation lines.
The diagonal (“HNC1”) channels reduce the pressure, redistribute the flow field, and create new TIM bifurcations corresponding to flow being distributed either to the edges of the chip or the channels (middle picture, Figure 1). Additional channels (“HNC2”) further sub-divide the flow, but the cross section of these second-level channels can be smaller because the maximum local pressure is lower. This leads to the hierarchical nature of the technology ? additional channels carry proportionally less TIM material and can have smaller cross sections. Bondline thickness (BLT) reduction due to the channels must offset the removal of highly-conductive solid material from the system. The hierarchical design ensures that the impact of removing solid is proportionately less for each additional channel “level”, corresponding to the proportionately lower impact of additional HNC levels on reducing BLT and assembly pressure.
We have characterized over 20 materials with HNC and found > 20% BLT reduction for up to three HNC levels (HNC3). The technology was first developed as a “TIM1” (silicon chip to lid) solution, but current work suggests even greater benefit on larger interfaces, for example, power electronics modules. On such 100 x larger areas, HNC can improve thermal performance without the effort and expense of qualifying and implementing newer paste formulations.